1. Field of the Invention
The present invention relates to interrupt handling apparatus and methods, and in particular to interrupt handling mechanisms which may deal with level sensitive interrupt requests and edge triggered interrupt messages.
2. Description of the Related Art
In modern computer systems, two different kinds of interrupts can be distinguished: level sensitive interrupts (or leveled triggered interrupts) and edge triggered interrupts. Generally speaking, level sensitive interrupts can be viewed to define a condition for an interrupt whereas edge triggered interrupts can be viewed as a discrete event.
Standard PCI (Peripheral Component Interconnect) functions and devices use level sensitive interrupts. Level sensitive interrupts can be shared by multiple I/O devices, meaning that multiple I/O devices can share the same interrupt line even though individually the interrupts from each device are discrete events. That is, multiple devices can all assert the line, and when a level sensitive interrupt occurs, the ISR (Interrupt Service Routine) must poll all the devices that are sharing the interrupt line.
Edge triggered interrupts are handled differently from level sensitive interrupts because a single edge triggered interrupt counts as a single occurrence of an event while level sensitive interrupts are conditions that exist. Modern bus concepts use e.g., MSI (Message Signal Interrupt) transport mechanisms to reduce the number of sideband signals. Message signal interrupts are edge triggered.
When servicing level sensitive interrupts in systems where interrupts are message based, i.e., edge triggered, a problem may arise in case multiple I/O devices share the same interrupt line. In particular, situations may exist where shared interrupts would cause only one interrupt message even if more than one interrupt source is active. Thus, an interrupt may get lost if it occurs during a time period in which a previous interrupt is still in service.